1. Field of the Invention
This invention generally relates to data processing systems, and more specifically, to frequency clocking in processor cores. Even more specifically, in the preferred embodiment, the invention relates to the analog multi-frequency clocking in multi-chip/multi-core processors.
2. Background Art
Servers are beginning to exploit a multiplicity of multi-core processor chips in order to continue to increase performance as processor frequency scaling can no longer meet the industry growth in performance. Also, the increasing difficulty and hardware cost, as well as signal integrity concerns, associated with the transmission of high frequency clocking throughout a multi-chip and multi-core processor server make this an untenable long-term strategy for future server systems. The state of the art for clock distribution is based on high-speed analog signals using transmission lines. This technique is limited in scalability due to skin effect, media and connector loss, crosstalk, termination mismatches, etc. Today's large servers contain, for example, greater than 10 processor chips typically containing two cores. It is expected that both chips and cores per chip will increase in the future. Transmission of high frequency clocks (>5-10 GHz) for multiple chips comprised of multiple cores is not feasible with known board technology and connectors. The need to operate this configuration in a tightly coupled mode, such as a Symmetric Multi-processor (SMP), will require a new clocking paradigm.
As microprocessor chips become larger with more cores, regional process and parameter variability across chip means that each core will have an optimal power/performance metric at a different chip voltage and clock frequency setting. Obtaining optimum performance for each core within a multi-core system is not feasible today. Separate core voltage domains are known and state-of-the-art but they can only serve to optimize the power at the chip level and not obtain optimum core performance. A server system with separate frequency domains per core is very complicated and is not practiced in the industry. For example, multiple off-chip and on-chip oscillators are required. Spread spectrum clocking used for EMI reduction with multiple oscillators makes “synchronous spreading” very difficult or impossible. Prior art technology is based on distribution of clocking signals across a wiring network known as a clock-tree. With the growth in the number of cores in multi-core microprocessors, clock-trees also grow into enormous complexity, creating serious chip layout design difficulties and translating into detractors to final product yield and related increase in manufacturing cost.